I wish our readers a 2015 filled up with personal and professional accomplishments!
Daniel Bayer from Cadence, brings the first article in a series that highlights constraint-modelling in Specman:
Cadence: Connected Field Sets – What Are Those and Why Should I Care?
Trent McClements from Invionics shows why combining macro definitions inside a package can be misleading:
Invionics: Packages and Macros Together? Watch Out!
Brian Murdock unfolds a long but true epic of how SystemVerilog’s fork and disable constructs may bring headache to anyone using them:
Brian Murdock: SystemVerilog Fork Disable “Gotchas”