We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints.
Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio.
Our consulting services range from functional and system-level verification to training and outsourcing. We provide services either on-site, at the client’s location, or off-site, and we are constantly striving to meet our clients’ communication and cost requirements. When it comes to off-site verification projects, we have the know-how and infrastructure to deliver excellent services while employing the highest security standards.
We provide ASIC and FPGA functional verification services spanning the entire coverage-driven verification flow from specification to coverage sign-off. Our consultants have the expertise to work on an entirely new verification project from beginning to end, as well as the skills and flexibility to engage with any critical points in your project.
We have extensive experience of all major hardware verification languages (HVLs) such as e-Language and SystemVerilog, and methodologies such as UVM, OVM, VMM, and eRM.
We are proficient in the use of all major EDA vendor tools, such as Cadence Incisive® Enterprise Simulator, the Synopsys VCS® functional verification solution and Mentor’s Questa® Advanced Simulator. We also use the Cadence® Palladium® series of accelerators/emulators, system-level modeling languages such as SystemC and tools like MATLAB®.
The AMIQ team is also able to help you with verification project management and 3rd party EDA vendor communication, including requirements specification and issue handling.
Due to the very high clock cycle consumption of System Level Verification, the planning and implementation of the verification process needs to be done carefully. The verification process requires in-depth planning, advanced verification skills like object-oriented language programming (SystemVerilog, C++/SystemC) and methodology awareness (UVM), as well as a creative approach to problem solving.
We have the expertise to provide system-level verification services for complex SoCs, involving working with various hardware and software IPs and using specific tools like hardware acceleration and hardware emulation.
Our experience with System Level Verification spans an extensive technical skills matrix, including:
We also have experience of System Level Verification management, including:
We have been successful at rescuing projects that have gone off track. We start by identifying the project bottlenecks. We then define a rescue strategy and implement it. We analyze performance periodically and continue to refine our strategy taking into account all internal and external factors until the project is back on track.
Our ramp-up services include infrastructure setup, template creation, methodology/flow definition and implementation, and resource planning. We can also perform interviews to assist with hiring new team members.
We can develop verification IPs (VIPs) on demand, for any protocol or function, by using any one of the HVLs (e, SystemVerilog) or assertion languages (SVA, PSL).
Normally, the client provides us with the protocol or function specification and we deliver the code, documentation, suites of tests, regression reports and scripts. The deliverables are prioritized according to client’s requirements and schedule in such a way that the integration work can start before the final release of the VIP.
Furthermore, our consultants can provide VIP integration and maintenance support.
We provide VIP qualification services that aim to ensure a VIP is functionally compliant with the protocol/functional specification, has generation capabilities that cover all required scenarios, contains correct checkers and includes relevant coverage items. We also verify that the architecture and implementation is compliant with a specific methodology, such as UVM.
We provide on-site and off-site training services for a broad range of hardware verification languages and methodologies. The training is delivered by senior consultants with comprehensive experience of working on a range of different projects with top companies.