• October, 21'st

    2016

    Authors

    Speaker

    Yet Another Memory Manager (YAMM) is a SystemVerilog library that provides support for memory based operations:

    • Buffers can be allocated following 6 allocation modes with any granularity or address alignment
    • Buffers can be inserted by user (non-overlapping)
    • Buffers can be deallocated either by address or by handle
    • Buffers can be searched for in the memory space by address or by handle
    • Buffers support payload, which can be assigned by the user, randomly generated, read and compared.
    • Implements a fast buffer search algorithm

    Beside these features YAMM provides debug facilities (e.g. memory map dump, usage statistics) and it is easy to integrate it with existing verification environments.

  • June, 28'th

    2016

    Authors

    Speaker

    Yet Another Memory Manager (YAMM) is a SystemVerilog library that provides support for memory based operations:

    • Buffers can be allocated following 6 allocation modes with any granularity or address alignment
    • Buffers can be inserted by user (non-overlapping)
    • Buffers can be deallocated either by address or by handle
    • Buffers can be searched for in the memory space by address or by handle
    • Buffers support payload, which can be assigned by the user, randomly generated, read and compared.
    • Implements a fast buffer search algorithm

    Beside these features YAMM provides debug facilities (e.g. memory map dump, usage statistics) and it is easy to integrate it with existing verification environments.

  • June, 23'rd

    2016

    Authors

    Speaker

    • Ionut Tolea

    Yet Another Memory Manager (YAMM) is a SystemVerilog library that provides support for memory based operations:

    • Buffers can be allocated following 6 allocation modes with any granularity or address alignment
    • Buffers can be inserted by user (non-overlapping)
    • Buffers can be deallocated either by address or by handle
    • Buffers can be searched for in the memory space by address or by handle
    • Buffers support payload, which can be assigned by the user, randomly generated, read and compared.
    • Implements a fast buffer search algorithm

    Beside these features YAMM provides debug facilities (e.g. memory map dump, usage statistics) and it is easy to integrate it with existing verification environments.

  • February, 29'th

    2016

    Speaker

    SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind:

    • decouple SVA test logic from SVA definition
    • simplify the creation of stimuli/checkers that validate the SVA
    • simplify test and stimuli maintenance

    SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog.

  • June, 25'th

    2015

    Speaker

    SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind:

    • decouple SVA test logic from SVA definition
    • simplify the creation of stimuli/checkers that validate the SVA
    • simplify test and stimuli maintenance

    SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog.

  • June, 23'rd

    2015

    Speaker

    SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind:

    • decouple SVA test logic from SVA definition
    • simplify the creation of stimuli/checkers that validate the SVA
    • simplify test and stimuli maintenance

    SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog.

  • April, 29'th

    2015

    Speaker

    SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind:

    • decouple SVA test logic from SVA definition
    • simplify the creation of stimuli/checkers that validate the SVA
    • simplify test and stimuli maintenance

    SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog.

  • October, 14'th

    2014

    Speaker

    Verification of high computational algorithmic RTL (e.g. digital signal processing) requires complex mathematical models that are hard to implement and slow to run in any of the existing hardware verification languages. Using numerical computing languages (e.g. Octave, Matlab) to code these models will dramatically speed up the verification sign-off by reuse of mathematical functions (e.g. predefined DSP functions) that are already verified. This also has a low risk of algorithm implementation bugs and guarantees optimal implementation for maximum simulation performance.

    This paper illustrates typical usage of external mathematical models inside the verification environment using SystemVerilog as the verification language and Octave, an open source sibling of Matlab, as the numerical modeling language.

  • May, 20'th

    2014

    Links

    We do pre-silicon verification in multiple iterations, each iteration including at least a regression. Regressions consume a great deal of HW resources (e.g. CPU time) and SW resources (e.g. licenses) and… a lot of human effort. This is what usually happens when we run a regression: we aim to reduce the time spent in regression analysis, especially when we run regressions at a fast pace, for example overnight. We want to see the results in a simple, easy to read report, as soon as possible. We are eager to start debugging issues immediately, instead of aggregating and organizing those tons of information resulting from running a regression. We expect everyone in the team to keep up to date on the regression status with virtually no effort. And in the long run, we want to have a history of regression’s progress.

    This poster shows a different way of dealing with these challenges using practical regression automation scripts. The scripts can help your team to save a lot of time and deal in an effective way with the regression results.

  • May, 20'th

    2014

    Links

    Authors

    Speaker

    If you want to cover a bus activity you can either use bit toggling or define coverage ranges as power-of-2 intervals. As bit toggling is not very relevant (can be covered very quickly in one transition from 0 to MAX_VALUE) the second option is preferred. But using power-of-2 coverage creates another problem: coverage intervals are uneven and covering the smaller bins takes a lot of time. In large projects it can take weeks of regressions time to fill all of them.

    This poster illustrates how the stimuli generation can be tweaked so that the smaller bins are hit just as often as the larger ones.