Recommended Articles

Recommended Articles – May 2017

Yet another way of connecting the testbench components to the interface containing the signals. Learn more about accessor classes and parametrization in the article How To Reduce the Number of VIP Instances using Accessor Classes We have a new entry on our radar: VerificationLand. Mark Glasser displays his view of an SVlogical way of writing […]

Horia-Răzvan Enescu

How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<)

The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures. This post is the first in a series of tutorials about packing and unpacking in SystemVerilog. The article’s sections are: Introduction 1. Pack bytes […]

Stefan Birman

How To Reduce the Number of VIP Instances using Accessor Classes

In this post I demonstrate how to use parameterization and accessor classes in order to reduce a variable number of VIP instances to a single VIP instance. The implementation I describe might improve the overall performance of the verification environment by reducing the number of threads and the amount of maintenance required (e.g. fewer instances, […]

Recommended Articles

Recommended Articles – April 2017

There are multiple ways of connecting a SystemVerilog interface instance to a virtual interface inside the verification environment. Cristian, described two ways of doing just that. One good old simple way when having just one interface instance and another one for multiple instances. CFSVision: UVM: How to Pass a Virtual Interface from Testbentch to Environment […]

Recommended Articles

Recommended Articles – March 2017

Using SystemVerilog along UVM methodology can be a difficult road for a newbie. Mentor together with Sandeep Nasa and Shankar Arora from Logic Fruit Technologies, have compiled a list of UVM tips&tricks that help you avoid some of the language traps and might improve performance. Read more on UVM Tips and Tricks Cadence has added […]

AMIQ Education Program

Mentoring Young Talent Through Hands-on Applications

Introduction by Stefan Birman This article doesn’t have too much to do with functional verification, but keep reading and you’ll be amazed at what a 3rd year student can achieve with the right kind of guidance. Răzvan was one of our 2016 Verification Summer Course participants. My attention was drawn by his ability to grasp […]