Recommended Articles

Recommended Articles – October 2016

New entry on our list: FPGASite is a nice resource for FPGA/VHDL enthusiasts. Claudio Avi Cham, the owner of the website, shows how to implement an arbiter in VHDL: FPGASite: VHDL Arbiter Part 1, Part 2, Part 3 What does a Functional Verification Engineer (FVE) do and how can you become an FVE? Stefan Birman, […]

Stefan Birman

Pre-Silicon Digital Functional Verification Engineer – The Job Description

This post (PDF version ) provides a technical overview of the job requirements for Pre-silicon Digital Functional Verification Engineer (FVE) positions. This post is complemented by a more in-depth post on the soft skills, joys and challenges of FVEs. Table of Contents Looking for a Good Start to Your Career? Your Chance to Be Part […]

AMIQ Consulting

amiq_i2c – ‘e’ Verification Component for I2C Protocol

AMIQ released the amiq_i2c eVC (e-Language Verification Component) on GitHub The eVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_i2c eVC is to model the I2C protocol, supporting all the features of the I2C protocol such as: multiple masters multiple slaves arbitration using SDA line […]

Recommended Articles

Recommended Articles – September 2016

Keisuke Shimizu, from ClueLogic, explains in his UVM tutorial series, how you can use register callbacks to implement side effects inside the UVM register model: ClueLogic: UVM Tutorial for Candy Lovers – 36. Register Callbacks Special attention should be payed to loop variables, as their behavior depends on how the array dimensions are specified at […]

Teo Vasilache

YAMM 2.0 Release is Available

Amiq is pleased to announce the release of the YAMM 2.0! The highlight of this release is a C++ implementation that provides the same API as the SystemVerilog one. Download Integrate YAMM with your C++ project Performance SystemVerilog Updates Roadmap Download You can download the YAMM library from GitHub. For getting up to speed you […]

Aurelian Ionel Munteanu

Gotcha: The Behavior of Foreach Loop Variables Depends on How the Array Dimensions Are Specified

In SystemVerilog the foreach statement can be used to iterate over the elements of an array. Special attention should be payed to loop variables (SystemVerilog IEEE 1800-2012 LRM Chapter 12.7.3, page 281), as their behavior depends on how the array dimensions are specified at declaration. For example: module tb; byte my_array[4:0]; initial begin automatic byte […]