AMIQ Education Program

Open Source Summer School Labs

The last Digital Circuits Simulation and Verification summer school made me wonder: why restrict access to the labs to only those students that can join the summer course? why not give access to the labs to any student that wished to take the course but couldn’t join due to various reasons? That is why I […]

AMIQ Education Program

Amiq Education Program Updates Summer 2017

I just came back from vacation and my fingers are restless, urging me to share with you some of the Amiq Education Program’s latest activities. First Generation of Students to Graduate under the Guidance of the AMIQ Education Program It’s celebration time: three students mentored under the AMIQ Education Program graduated at the beginning of […]

Recommended Articles

Recommended Articles – July 2017

 Tudor (Verification Gentleman) continues his series of articles on unit testing with a case study on Testing SVA Properties and Sequences.  Ben Cohen (SystemVerilog.us) goes into details on how tasks and threads are used inside System Verilog Assertions. The Understanding the SVA Engine + Simple alternate solutions article also includes an SVA example that is […]

Teo Vasilache

How To Automate Code Coverage analysis with Coverage Lens

Sometimes code coverage is required to finalize the verification. By running only random tests most designs will be left with uncovered sections. Trying to fill up the last bits of code coverage you end up either writing directed tests to reach corner cases, or excluding certain “unreachable” sections from coverage statistics. Writing directed tests to […]

Recommended Articles

Recommended Articles – June 2017

UVM provides callbacks mechanism that allows one to expand code’s functionality. Munjal explains advanced usage of callbacks in UVM. You might remember, from the highlights of DVCon US 2017 conference, that we recommended a paper about constrained random and dynamic seed manipulation (“Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding […]

Horia-Răzvan Enescu

How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)

In this post I show how to use the streaming operators to unpack data into variables or data structures in SystemVerilog. This is the second part of a 3-post series on data packing/unpacking operations and the natural follow-up to the first part that focuses on packing data using streaming operators. The unpacking operation is the […]