Recommended Articles

Recommended Articles – December 2016

Often, it happens that the information about a Design Under Test (DUT) or about its verification is being organized in the form of a table like structure (configurations, registers, operation modes, traffic types, etc.). Imagine if you could automatically create bits of code from an Excel table. How awesome is that! E-language is now able […]

Daniel Ciupitu

To be or not to be a Verification Engineer

A verification engineer builds verification environments used to hunt for hardware design flaws and prove a product will operate as expected. But what does that really mean? Do you have the skills to do this job? And should someone even consider doing it? This post is a follow-up to Stefan’s job description of a verification […]

Recommended Articles

Recommended Articles – November 2016

Every design or verification engineer needed at some point in time a basic compile/run script. Go2UVM presents a basic compile/run script that supports all 4 major simulators (Incisive, VCS, QuestaSim and RivieraPro): Go2UVM: Generic Makefile for UVM simulations Go2UVM shows the basics of using variable delays in SystemVerilog Assertions: GO2UVM: Handling variable delays in SystemVerilog […]

Ionuț Ciocîrlan

Highlights of DVCon Europe 2016

The third edition of DVCon Europe (October 19-20, 2016, Munich) has just come to an end. The technical content of the conference was diverse, but three primary areas of interest could be identified: portable stimulus, formal verification, and automotive. While the first two are already common themes in conference programs, the automotive field has recently […]

AMIQ Education Program

Pre-Silicon Verification Course at Politehnica University of Timișoara

I am proud to announce an exciting new development in the Romanian higher education system: Oana Boncalo, Assistant Professor in the Computer Engineering Department, Politehnica University of Timișoara, has begun teaching the Verification and Validation of Hardware Systems, a course that introduces students to pre-silicon digital hardware verification methods. I think this is the first […]

Stefan Birman

Functional Coverage Patterns: The Counter

This post explains the functional verification of counters and it is part of a series of posts exploring functional coverage patterns. The first post in the series was Functional Coverage Patterns: Bitwise Coverage. Table of contents What is a Counter? Counter Verification Regarding Synchronicity Reset Value Coverage Clear Value Coverage Overflow and Underflow Policy Coverage […]