Stefan Birman

How To Read a Specification

I consider that spec reading and comprehension is a critical part of the verification flow. All following stages in a verification project depend on this activity and that’s why every junior engineer who joins AMIQ goes first through a specification reading crash course. I present below a set of guidelines that AMIQ engineers follow. Enjoy! […]

Recommended Articles

Recommended Articles – March 2015

The Spring is here! We offer you a nice, hand-picked, bouquet of articles. Sean Eron Anderson saves us from the marsh of bitwise operations. He compiled a list of techniques, algorithms, operations, functions that one could do to pull oneself up: Standford: Bit Twiddling Hacks The Gentleman presents his view on the good, ol’ topic […]

AMIQ Consulting

amiq_dcr – SystemVerilog UVC for DCR Protocol

AMIQ released the amiq_dcr UVC on GitHub The UVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_dcr UVC is to model the Device Control Register Bus (DCR) protocol, supporting all the features of the protocol such as: 4-cycle minimum read or write transfers extendable by […]

AMIQ Consulting

amiq_apb – SystemVerilog UVC for APB Protocol

We release amiq_apb UVC to the verification community under the Apache License 2. amiq_apb UVC implements the APB protocol and it features: Supports the full APB protocol specification: one master-multiple slaves, transfers with wait states, slave error response, access protection HTML API documentation included Verification plans included Self checking tests Usage examples UVM-1.2 Compliant We […]

Recommended Articles

Recommended Articles – February 2015

Although February was a 28 days month the Verification community was more active than on a 31 days month. The random generation strategy could be the root cause of long time required to achieve coverage closure. Claudia provides a use case scenario for evaluating coverage closure in relation to generation strategy: AMIQ Blog: A Coverage […]

Cristian Slav

Gotcha: Function Calls in SystemVerilog Constraints

SystemVerilog allows to call functions inside constraints, although, as I found out, it is a sensitive topic. Here is an example: class constraint_container; rand int unsigned a, b, c; function int unsigned get_a(); return a; endfunction function int unsigned value_of(int unsigned value); return value; endfunction constraint a_constraint { a == 5; // I expect “b” […]