Recommended Articles

Recommended Articles – October 2014

Working in a multi-language environment makes you hit this scenario: I model some data using a “when” subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here: Cadence: Transferring e “when” Subtypes to UVM SV via TLM Ports—UVM-ML OA Package When you wonder […]

AMIQ Consulting

amiq_eth – The Ethernet Packet Library for SystemVerilog and SystemC

AMIQ released the amiq_eth verification library on GitHub, the hotspot for Open Source projects. The library is available to the verification community for free under the Apache License 2. The purpose of the amiq_eth library is to define all Ethernet packets as a basis for virtual verification IPs that target Ethernet upper layers. It includes […]

Stefan Birman

How to print `timescale in Verilog, SystemVerilog and VHDL

Sometimes you need to make sure the correct time unit and precision are applied for each module down the instance tree, especially when there are different timescale directives in different modules and timescale arguments are used. Print `timescale in Verilog, SystemVerilog Use $printtimescale(path) simulator directive: // timescale `timescale 1ns/10ps // top testbench module module tb(); […]

Stefan Birman

Attend Algorithm Verification Tutorial at DVCon Europe

We will be participating at DVCon Europe on October 14-15, 2014, in Munich. Two of our consultants will be presenting in the Tutorial section, on October 14, 2014 at 16:00. Daniel Ciupitu and Andra Socianu will guide you through efficient algorithm verification using SystemVerilog and Open Source Software. Beside the step-by-step tutorial, you will also […]

Recommended Articles

Recommended Articles – September 2014

SystemVerilog does not support multiple class inheritance, but there are ways to emulate it. Tudor Timisescu shows one way: VerificationGentleman: Fake It ’til You Make It – Emulating Multiple Inheritance in SystemVerilog Is your verification environment using multi-language verification components? Do you need to synchronize the end of test objections? Cadence illustrates how to sync […]

Alexandru Marin

What Goes where in SystemVerilog?

Is it legal SystemVerilog syntax to declare a class inside a program? What about a function inside a generate block? The table below summarizes the syntactically legal combinations (marked with a check ✔ sign). The number of possible combinations is astonishing. And yet I bet some of the valid combinations have never crossed your mind! On the […]