Cristian Slav

Gotcha: Using “rand” Modifier for Object Handles is not enough!

SystemVerilog allows rand modifier to be used for object handles and the object will be randomized only if it is not null. The “gotcha” is that, depending on the simulator, no error or warning will be issued if you forget to initialize the randomized object. Here is an example that illustrates the gotcha: class item; […]

Recommended Articles

Recommended Articles – April 2015

Reading a specification is a continuous process that anyone can learn. Stefan guides you through the steps of this process: AMIQ Blog: How to Read a Specification: You can draw a picture without lifting the pencil by using constraint random generation: VerificationGentleman: Fun and Games with CRV: Draw This Without Lifting Your Pencil Writing assertions […]

AMIQ Consulting

How to Verify SystemVerilog Assertions with SVAUnit

A version of this article, titled SystemVerilog Assertions Verification with SVAUnit, was presented at CDNLive EMEA 2015 by Andra Socianu and Ionut Ciocirlan. Intro SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizeable, non-intrusive, coverable), we must verify they […]

Stefan Birman

How To Read a Specification

I consider that spec reading and comprehension is a critical part of the verification flow. All following stages in a verification project depend on this activity and that’s why every junior engineer who joins AMIQ goes first through a specification reading crash course. I present below a set of guidelines that AMIQ engineers follow. Enjoy! […]

Recommended Articles

Recommended Articles – March 2015

The Spring is here! We offer you a nice, hand-picked, bouquet of articles. Sean Eron Anderson saves us from the marsh of bitwise operations. He compiled a list of techniques, algorithms, operations, functions that one could do to pull oneself up: Standford: Bit Twiddling Hacks The Gentleman presents his view on the good, ol’ topic […]

AMIQ Consulting

amiq_dcr – SystemVerilog UVC for DCR Protocol

AMIQ released the amiq_dcr UVC on GitHub The UVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_dcr UVC is to model the Device Control Register Bus (DCR) protocol, supporting all the features of the protocol such as: 4-cycle minimum read or write transfers extendable by […]