Recommended Articles

Recommended Articles – December 2014

I wish our readers a 2015 filled up with personal and professional accomplishments! Daniel Bayer from Cadence, brings the first article in a series that highlights constraint-modelling in Specman: Cadence: Connected Field Sets – What Are Those and Why Should I Care? Trent McClements from Invionics shows why combining macro definitions inside a package can […]

Cristian Slav

How to Inspect Ethernet Packet Streams with Wireshark

Many protocol stacks in SoCs are based on the IEEE 802.3 Ethernet protocol as the data link layer, while the upper layers can be standard or application specific. Therefore, verification engineers have to inspect and debug Ethernet packet streams generated or monitored by the verification environment. This article shows how to connect the Wireshark network […]

Recommended Articles

Recommended Articles – November 2014

Tudor recommends us to take advantage of the e-language features to define similar vr_ad registers instead of using copy/paste: VerificationGentleman: Experimental Cures for Flattened Register Definitions in vr_ad Then he shows us how to implement side effects of read/write operations using vr_ad’s indirect_access() method: VerificationGentleman: Using indirect_access(…) in vr_ad The same Gentleman tutors us on […]

Stefan Birman

A Birds-Eye View of DVCon Europe

I finally found some time to write about the first edition of DVCon-Europe, which took place on 14-15th of October, 2014, in Munich. The content What I liked most at DVCon Europe was conference’s focus on content that addressed interesting and often intriguing technical topics. Below you can find the summary for a few presentations […]

Andra Socianu, Daniel Ciupitu

How to Connect SystemVerilog with Octave

When we must verify a highly computational RTL, we may deal with complicated mathematical functions and algorithms. Implementing and debugging an RTL model can be tricky and time consuming. In such cases modeling using Octave/Matlab, C/C++ or SystemC can be a good alternative. In this article we present a “Hello world!” example to illustrate how […]

Recommended Articles

Recommended Articles – October 2014

Working in a multi-language environment makes you hit this scenario: I model some data using a “when” subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here: Cadence: Transferring e “when” Subtypes to UVM SV via TLM Ports—UVM-ML OA Package When you wonder […]