Blog | AMIQ Consulting

Teo Vasilache
Verification Engineer

C++ Implementation of Functional Coverage for SystemC

February 22nd, 2018
2 Comments

We release Functional Coverage for SystemC (FC4SC) library which provides mechanisms for functional coverage definition, collection and reporting. FC4SC is a header-only, C++2011-based library, that can be integrated with C++ applications, including SystemC models. It’s primary use case is to measure the level of exercise of SystemC models, basically to measure how many of model’s […]

CPP , functional coverage , GitHub , SystemC , utility library

Andrei Vintilă
Verification Engineer

YAMM – Yet Another Memory Manager

July 12th, 2016
No Comments

Ionut Tolea and Andrei Vintila presented the paper Yet Another Memory Manager (YAMM) at SNUG Conference 2016 – Munich. The code of YAMM library is released to the public using AMIQ’s GitHub repository. YAMM Overview Basic Concepts Usage examples Initialization Buffer insertion, buffer allocation and buffer type Buffer search and buffer deallocation Buffer content operations […]

functional verification , GitHub , methodology , SystemVerilog , utility library , YAMM

Mihai Stoian
Verification Engineer

Physical Coding Library

February 25th, 2016
No Comments

AMIQ released the Physical Coding Library on GitHub. The Physical Coding Library provides SystemVerilog/UVM implementations of line coding schemes that are common to all major high speed communication protocols: Ethernet, RapidIO, DisplayPort, SATA, USB3.0, PCI Express etc. These are the supported line coding schemes: 8b/10b encoding 64b/66b encoding additive scrambling with parameterizable LFSR multiplicative scrambling […]

64b66b encoding , 8b10b encoding , algorithms , IEEE802.3 , scrambler , utility library , VIP

AMIQ Consulting
Verification Engineer

How to Verify SystemVerilog Assertions with SVAUnit

April 29th, 2015
12 Comments

A version of this article, titled SystemVerilog Assertions Verification with SVAUnit, was presented at CDNLive EMEA 2015 by Andra Socianu and Ionut Ciocirlan. Intro SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizeable, non-intrusive, coverable), we must verify they […]

functional verification , GitHub , how to , methodology , SVAUnit , SystemVerilog , SystemVerilogAssertion , utility library

Cristian Slav
Verification Engineer

How to Inspect Ethernet Packet Streams with Wireshark

January 14th, 2015
No Comments

Many protocol stacks in SoCs are based on the IEEE 802.3 Ethernet protocol as the data link layer, while the upper layers can be standard or application specific. Therefore, verification engineers have to inspect and debug Ethernet packet streams generated or monitored by the verification environment. This article shows how to connect the Wireshark network […]