Recommended Articles

Recommended Articles – February 2017

Solving sudoku is fun. Solving sudoku using SystemVerilog is both fun and instructive. In a 2015 article, Keisuke Shimizu from ClueLogic, provided a SystemVerilog solution for solving sudoku. In the 2017 version he provides a different solution that makes use of “unique” SystemVerilog keyword. Read all about it here: Hidden Gems of SystemVerilog – 4. […]

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Recommended Articles – January 2017

SystemVerilog standard provides structure and union data types. Jason Yu, from Intel, has tried to use them for RTL design and he shared his experience via this VerilogPro article: Using SystemVerilog Structures and Unions in a Design. AMIQ Consulting created an UVM/SystemVerilog application that exports existing UVM register models to an IP-XACT file in order […]

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Recommended Articles – December 2016

Often, it happens that the information about a Design Under Test (DUT) or about its verification is being organized in the form of a table like structure (configurations, registers, operation modes, traffic types, etc.). Imagine if you could automatically create bits of code from an Excel table. How awesome is that! E-language is now able […]

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Recommended Articles – November 2016

Every design or verification engineer needed at some point in time a basic compile/run script. Go2UVM presents a basic compile/run script that supports all 4 major simulators (Incisive, VCS, QuestaSim and RivieraPro): Go2UVM: Generic Makefile for UVM simulations Go2UVM shows the basics of using variable delays in SystemVerilog Assertions: GO2UVM: Handling variable delays in SystemVerilog […]

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Recommended Articles – October 2016

New entry on our list: FPGASite is a nice resource for FPGA/VHDL enthusiasts. Claudio Avi Cham, the owner of the website, shows how to implement an arbiter in VHDL: FPGASite: VHDL Arbiter Part 1, Part 2, Part 3 What does a Functional Verification Engineer (FVE) do and how can you become an FVE? Stefan Birman, […]

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Recommended Articles – September 2016

Keisuke Shimizu, from ClueLogic, explains in his UVM tutorial series, how you can use register callbacks to implement side effects inside the UVM register model: ClueLogic: UVM Tutorial for Candy Lovers – 36. Register Callbacks Special attention should be payed to loop variables, as their behavior depends on how the array dimensions are specified at […]