Recommended Articles

Recommended Articles – November 2018

New data arrived from the 2018 Wilson Research Group Functional Verification Study. This research is done every two years and it shows trends in our functional verification domain. If you are interested in the data you can read the set of articles that will follow on verification horizons. Here are the first ones: Prologue, Part […]

Recommended Articles

Recommended Articles – October 2018

Cristian from CFSVision wrote a short tutorial on how to work with SystemVerilog queues. Cadence published a new article in the series regarding SystemVerilog code optimizations. This time it tackles the subject of creating and managing dynamic objects. AnySilicon published an article aiming to describe the stages of ASIC production. The big picture always helps […]

Recommended Articles

Recommended Articles – September 2018

In case of e-language it is the aspect oriented-nature of the language itself that helps cutting down the compile and simulation rerun time. You can read more about dynamic load or just-in-time patching: Adding a Patch Just in Time!. I always try to find ways of shortening the time it takes to wait for various […]

Recommended Articles

Recommended Articles – August 2018

In his article about how to avoid FIFO overflows, Stefan promised a second solution. Here is part II of the article presenting the solution which makes use of uvm constructs. Neil from AgileSOC continues to simplify the SVAUnit framework. He makes use of his new mocking framework in order to decouple the driver from the […]

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Recommended Articles – July 2018

AMIQ Education Program saga continues…. This years’ summer school received more attention from the students according to Stefan’s feedback: Digital Circuits Simulation and Verification Summer School. FIFOs are encountered in many digital designs and the verification of such designs comes with specific challenges, one of them being to protect the FIFOs against overflow. You can […]

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Recommended Articles – June 2018

We present to you the SystemVerilog and VHDL Grammars in HTML format. The grammars represent the BNF (Backus-Naur Form) notation in an HTML format, with hyperlinks, anchors and tooltips. You can also download them from the GitHub repository. John Neil, from AgileSOC, continues his reflection on how verification engineers should think about their testbench code: […]