Recommended Articles

Recommended Articles – March 2019

Cristian Bob (AMIQ) leveraged the power of Python into a SystemVerilog testbench using a client-server architecture. The post How to Connect SystemVerilog with Python is a must-read if you use or plan to use Python along with SystemVerilog. It is natural to see Python infiltrating the verification world given it’s popularity (see TIOBE index) and […]

Recommended Articles

Recommended Articles – February 2019

It looks like February is a short month and probably people were focused more on preparing for the DvCon US 2019 conference. Let’s meet again in March with new and interesting technical content from our domain. In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, papers and the list of blogs we […]

Recommended Articles

Recommended Articles – January 2019

New entry on our list. Recently, I found a new source of interesting papers related to UVM and Verification. It is the Rochester Institute of Technology (RIT) Scholar Works. RIT is a tech University from New-York, USA. Of particular interest are the theses papers published on their website. Here are some papers which tackle various […]

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Recommended Articles – December 2018

Sergiu Duda from AMIQ has put a lot of effort into creating a high quality article on the non-trivial topics of High Level Synthesis and Deep Learning. The later, is not found in the everyday terminology of a verification engineer. Deep learning is just a flavour of a bigger part called Machine Learning which in […]

Recommended Articles

Recommended Articles – November 2018

New data arrived from the 2018 Wilson Research Group Functional Verification Study. This research is done every two years and it shows trends in our functional verification domain. If you are interested in the data you can read the set of articles that will follow on verification horizons. Here are the first ones: Prologue, Part […]

Recommended Articles

Recommended Articles – October 2018

Cristian from CFSVision wrote a short tutorial on how to work with SystemVerilog queues. Cadence published a new article in the series regarding SystemVerilog code optimizations. This time it tackles the subject of creating and managing dynamic objects. AnySilicon published an article aiming to describe the stages of ASIC production. The big picture always helps […]