Recommended Articles

Recommended Articles – November 2020

AMIQ has published a new set of verification resources. Cheatsheets for SystemVerilog and for SystemVerilog Assertions. When in need, every verification engineer now has a reference where to quickly search for basic information. SystemVerilog and SVA Cheatsheet Manish, from Learn UVM Verification, continues his series on UVM RAL. This time he shows how to implement […]

Recommended Articles

Recommended Articles – October 2020

AMIQ has released a new UVC that facilitates register accesses. It is called Register Agent: Register Agent: A UVC for Register Access. Manish from Learn UVM Verification explains why we need a UVM Register Abstraction Layer: Why UVM RAL is needed?. Cadence released a new feature that allows you to integrate Python code into e-language. […]

Recommended Articles

Recommended Articles – September 2020

Did you know that you can match strings using regular expressions from within SystemVerilog code? UVM implements a function called uvm_re_match. My colleague, Florin Oancea, explains how to use it and what you should pay attention at: How to Match Strings in SystemVerilog Using Regular Expressions In the August edition of the recommended articles I […]

Recommended Articles

Recommended Articles – August 2020

Ioana Cristea from Amiq shows how to achieve a non blocking communication between the SystemVerilog simulator and an external component, like Python: Non-Blocking Socket Communication in SystemVerilog Using DPI-C. Neil Johnson and Dave Rich have launched a challenge to the verification community. Discover and fix race conditions inside 10 SystemVerilog code snippets. Read more in […]

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Recommended Articles – July 2020

Neil Johnson announced he will take a step back and pass the leadership of SVUnit project to Tudor Timisescu, aka Verification Gentleman. SVUnit is a consistent and valuable contribution to the verification community and I am happy it is not lost. That’s the OpenSource spirit at work! Welcome back Manish! After four years of silence, […]

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Recommended Articles – June 2020

SystemVerilog Multidimensional Arrays is a juicy topic for a blog post given they are feature reach. Here is a post that explains some of the features: SystemVerilog Multidimensional Arrays A long-awaited feature comes into existence: adjusting verification environment behavior based on collected coverage items in real time at run time. Specman team facilitates this operation […]