- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – September 2016
- September 29th, 2016
- No Comments
Keisuke Shimizu, from ClueLogic, explains in his UVM tutorial series, how you can use register callbacks to implement side effects inside the UVM register model: ClueLogic: UVM Tutorial for Candy Lovers – 36. Register Callbacks Special attention should be payed to loop variables, as their behavior depends on how the array dimensions are specified at […]
- Aurelian Ionel Munteanu
- Verification Engineer
Gotcha: The Behavior of Foreach Loop Variables Depends on How the Array Dimensions Are Specified
- August 31st, 2016
- 1 Comment
In SystemVerilog the foreach statement can be used to iterate over the elements of an array. Special attention should be payed to loop variables (SystemVerilog IEEE 1800-2012 LRM Chapter 12.7.3, page 281), as their behavior depends on how the array dimensions are specified at declaration. For example: module tb; byte my_array[4:0]; initial begin automatic byte […]
- Aurelian Ionel Munteanu
- Verification Engineer
Gotcha: “static” function/task in SystemVerilog
- August 5th, 2016
- 8 Comments
While working with static methods from SystemVerilog I found a non-intuitive behaviour that I would like to share with you. I could not find it documented anywhere within the SystemVerilog LRM. What do static and its automatic counterpart mean? In SystemVerilog IEEE 1800-2012 LRM (Chapter 8.10 page 141), a static method is defined as: “A […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – June 2016
- June 27th, 2016
- No Comments
Implementing coverage in SystemVerilog can become a challenging task. Horia presents the last article from a series of 3, on how to implement flexible coverage. AMIQ: How to Implement Flexible Coverage Definitions (Part 3) Henry Chan presents a high level overview of the uvm_reg package: SemiEngineering: UVM Register Layer: The Structure Here it is a […]
- Aurelian Ionel Munteanu
- Verification Engineer
Gotcha: Access an out of Bounds Index for a SystemVerilog Fixed Size Array
- January 26th, 2016
- No Comments
I came across a SystemVerilog coding scenario where extra precaution needs to be taken when accessing fixed size arrays. The scenario was about accessing an invalid index in a fixed size array. SystemVerilog defines invalid index values as such: ‘X’ (undefined), ‘Z’ (high impedance), a value higher than the array’s size or a negative value. […]
- AMIQ Consulting
- Verification Engineer
Gotcha: Using a==b==c in SystemVerilog Constraints
- September 30th, 2015
- No Comments
Looking over verification forums, I found a thread where the author was wondering how does a==b==c constraint get evaluated since the result was not the one he was expecting. The scenario is like this: three variables need to be randomized and you want to constraint them to the same value. If you are thinking to […]
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