Stefan Birman

How To Customize UVM Sequencer’s Arbitration Policy

This post shows how you can implement a custom sequencer arbitration policy in UVM. The example considers a sequence that contains a field called seq_type: typedef enum {MASTER_SEQ, REQ_SEQ, CNFRM_SEQ, ACK_SEQ, REDO_SEQ, DATA_SEQ } ex_seq_type_t; class ex_base_sequence extends uvm_sequence#(ex_sequence_item); ex_seq_type_t seq_type; // this field is used by the arbitration scheme …….. endclass The arbitration policy […]

AMIQ Education Program

Amiq Education Program Updates Summer 2017

I just came back from vacation and my fingers are restless, urging me to share with you some of the Amiq Education Program’s latest activities. First Generation of Students to Graduate under the Guidance of the AMIQ Education Program It’s celebration time: three students mentored under the AMIQ Education Program graduated at the beginning of […]

Stefan Birman

Highlights of DVCon US 2017

DVCon US (Feb 27-Mar 2 2017, San Jose, California) has come to an end after another content-rich edition. Some of the highlights of the technical program AMIQ consultants enjoyed attending are provided below. Hot Topics The main highlight of the conference by far was the emerging Portable Stimulus Standard (PSS), which was presented through a […]

Andrei Apostoae

SVAUnit 3.2 Release is Available

AMIQ is pleased to announce version 3.2 of the SVAUnit framework! Highlights of SVAUnit 3.2 are: Added an SVAUnit User Guide with complete examples Added setup_test() task Updated checks API Fixed check evaluation timing to be more accurate Fixed printed messages Support for HTML regression report Fixed assertion registration issue Let’s go through the details […]

Daniel Ciupitu

To be or not to be a Verification Engineer

A verification engineer builds verification environments used to hunt for hardware design flaws and prove a product will operate as expected. But what does that really mean? Do you have the skills to do this job? And should someone even consider doing it? This post is a follow-up to Stefan’s job description of a verification […]

Stefan Birman

Pre-Silicon Digital Functional Verification Engineer – The Job Description

This post (PDF version ) provides a technical overview of the job requirements for Pre-silicon Digital Functional Verification Engineer (FVE) positions. This post is complemented by a more in-depth post on the soft skills, joys and challenges of FVEs. Table of Contents Looking for a Good Start to Your Career? Your Chance to Be Part […]