Stefan Birman

Functional Coverage Patterns: The Counter

This post explains the functional verification of counters and it is part of a series of posts exploring functional coverage patterns. The first post in the series was Functional Coverage Patterns: Bitwise Coverage. Table of contents What is a Counter? Counter Verification Regarding Synchronicity Reset Value Coverage Clear Value Coverage Overflow and Underflow Policy Coverage […]

Recommended Articles

Recommended Articles – June 2016

Implementing coverage in SystemVerilog can become a challenging task. Horia presents the last article from a series of 3, on how to implement flexible coverage. AMIQ: How to Implement Flexible Coverage Definitions (Part 3) Henry Chan presents a high level overview of the uvm_reg package: SemiEngineering: UVM Register Layer: The Structure Here it is a […]

Horia-Răzvan Enescu

How to Implement Flexible Coverage Definitions (Part 3)

In the final part of this 3-post series (Part 1, Part 2), I will show a way of covering enum transitions and conditionally ignoring transitions to and from certain enum values. For example, in the case of a CPU’s instruction set, you want to make sure that all possible combinations of two consecutive instructions are […]

Horia-Răzvan Enescu

How to Implement Flexible Coverage Definitions (Part 2)

In part 1 of this 3-post series, I presented a way of defining flexible coverage definitions in SystemVerilog using the with clause. In this second post, I will show a way of achieving the same flexibility for transition coverage. As SystemVerilog’s grammar doesn’t allow us to use the with clause for defining transition bins, we […]

Horia-Răzvan Enescu

How to Implement Flexible Coverage Definitions (Part 1)

In the first part of this 3-post series, I would like to show a compact way of defining flexible coverage in SystemVerilog that adapts to a variable parameter. Let’s consider the case where you need to cover the size of a burst, which can range between 1..max, with max being configurable within 1..N. The bins […]

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Recommended Articles – September 2015

SystemVerilog interfaces are rigid constructs that don’t offer the flexibility of a class (e.g. polymorphism). Tudor Timisescu presents a recipe to create flavors of an interface, recipe which avoids turning the interface into a big, monolithic structure: VerificationGentleman: On SystemVerilog Interface Polymorphism and Extendability Did you ever think of functional coverage patterns?Well, our colleague Stefan […]