Recommended Articles

Recommended Articles – February 2017

Solving sudoku is fun. Solving sudoku using SystemVerilog is both fun and instructive. In a 2015 article, Keisuke Shimizu from ClueLogic, provided a SystemVerilog solution for solving sudoku. In the 2017 version he provides a different solution that makes use of “unique” SystemVerilog keyword. Read all about it here: Hidden Gems of SystemVerilog – 4. […]

Recommended Articles

Recommended Articles – December 2016

Often, it happens that the information about a Design Under Test (DUT) or about its verification is being organized in the form of a table like structure (configurations, registers, operation modes, traffic types, etc.). Imagine if you could automatically create bits of code from an Excel table. How awesome is that! E-language is now able […]

Recommended Articles

Recommended Articles – October 2016

New entry on our list: FPGASite is a nice resource for FPGA/VHDL enthusiasts. Claudio Avi Cham, the owner of the website, shows how to implement an arbiter in VHDL: FPGASite: VHDL Arbiter Part 1, Part 2, Part 3 What does a Functional Verification Engineer (FVE) do and how can you become an FVE? Stefan Birman, […]

AMIQ Consulting

amiq_i2c – ‘e’ Verification Component for I2C Protocol

AMIQ released the amiq_i2c eVC (e-Language Verification Component) on GitHub The eVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_i2c eVC is to model the I2C protocol, supporting all the features of the I2C protocol such as: multiple masters multiple slaves arbitration using SDA line […]

Recommended Articles

Recommended Articles – July 2016

Manish Singhal, from LearnUVMVerification, presents a list of advantages of using assertions and describes the arbitration mechanism of UVM Sequences. Keisuke Shimizu, from ClueLogic, shows how to dump transactions into a file using UVM do_record(). He also gives an overview of component overrides in UVM. A short and practical article from Bryan Murdock on streaming […]

Recommended Articles

Recommended Articles – February 2016

Anders Nordstrom has written one of the best articles I’ve read about the effects of over-constraining properties in formal verification. The author describes what’s safe to do and what’s not safe to do when using formal methodologies: EDN: Anders Nordstrom: Don’t over-constrain in formal property verification (FPV) flows High speed serial communication protocols like Ethernet, […]