- Cristian Bob
- Verification Engineer
How to Connect e-Language with Python
- May 17th, 2019
- No Comments
This post is an addition to the previous post How to connect SystemVerilog with Python. The principles of connecting e-Language with Python are similar to those presented in the aforementioned post. Table of contents Create the e-Language-to-C Interface Client Layer Code Changes Create the Top Modules How To Run the Example Create the e-Language-to-C Interface […]
- DPI-C , e-Language , how to , Python
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – March 2017
- March 31st, 2017
- No Comments
Using SystemVerilog along UVM methodology can be a difficult road for a newbie. Mentor together with Sandeep Nasa and Shankar Arora from Logic Fruit Technologies, have compiled a list of UVM tips&tricks that help you avoid some of the language traps and might improve performance. Read more on UVM Tips and Tricks Cadence has added […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – February 2017
- February 24th, 2017
- No Comments
Solving sudoku is fun. Solving sudoku using SystemVerilog is both fun and instructive. In a 2015 article, Keisuke Shimizu from ClueLogic, provided a SystemVerilog solution for solving sudoku. In the 2017 version he provides a different solution that makes use of “unique” SystemVerilog keyword. Read all about it here: Hidden Gems of SystemVerilog – 4. […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – December 2016
- December 22nd, 2016
- No Comments
Often, it happens that the information about a Design Under Test (DUT) or about its verification is being organized in the form of a table like structure (configurations, registers, operation modes, traffic types, etc.). Imagine if you could automatically create bits of code from an Excel table. How awesome is that! E-language is now able […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – October 2016
- October 31st, 2016
- 1 Comment
New entry on our list: FPGASite is a nice resource for FPGA/VHDL enthusiasts. Claudio Avi Cham, the owner of the website, shows how to implement an arbiter in VHDL: FPGASite: VHDL Arbiter Part 1, Part 2, Part 3 What does a Functional Verification Engineer (FVE) do and how can you become an FVE? Stefan Birman, […]
- AMIQ Consulting
- Verification Engineer
amiq_i2c – ‘e’ Verification Component for I2C Protocol
- October 7th, 2016
- No Comments
AMIQ released the amiq_i2c eVC (e-Language Verification Component) on GitHub The eVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_i2c eVC is to model the I2C protocol, supporting all the features of the I2C protocol such as: multiple masters multiple slaves arbitration using SDA line […]
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