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AMIQ Consulting
Verification Engineer

SystemVerilog and VHDL Grammars in HTML format

April 30th, 2018
2 Comments

We share with the verification community the SystemVerilog and VHDL language grammars in browsable HTML format. The HTML grammars are based on SystemVerilog LRM 2012 (IEEE Std 1800TM-2012) and VHDL LRM 2008 (IEEE Std 1076TM-2008). You can browse these online on their dedicated page Resource > Grammars. You can also download them for off-line use […]

IEEE1800 Standard , SystemVerilog , SystemVerilogAssertion , Verilog , VHDL

Stefan Birman
Verification Engineer

How to print `timescale in Verilog, SystemVerilog and VHDL

October 31st, 2014
2 Comments

Sometimes you need to make sure the correct time unit and precision are applied for each module down the instance tree, especially when there are different timescale directives in different modules and timescale arguments are used. Print `timescale in Verilog, SystemVerilog Use $printtimescale(path) simulator directive: // timescale `timescale 1ns/10ps // top testbench module module tb(); […]