How to print `timescale in Verilog, SystemVerilog and VHDL

• October 31st, 2014
• 2 Comments

Sometimes you need to make sure the correct time unit and precision are applied for each module down the instance tree, especially when there are different timescale directives in different modules and timescale arguments are used. Print `timescale in Verilog, SystemVerilog Use $printtimescale(path) simulator directive: // timescale `timescale 1ns/10ps // top testbench module module tb(); […]

• how to , SystemVerilog , Verilog , VHDL