Andrei Apostoae

SVAUnit 3.2 Release is Available

AMIQ is pleased to announce version 3.2 of the SVAUnit framework! Highlights of SVAUnit 3.2 are: Added an SVAUnit User Guide with complete examples Added setup_test() task Updated checks API Fixed check evaluation timing to be more accurate Fixed printed messages Support for HTML regression report Fixed assertion registration issue Let’s go through the details […]

Stefan Birman

A Conference to Attend: Forum on Specification and Design Languages

Between 14-15th of September I attended the Forum on Specification and Design Languages(FDL) in Barcelona, a niche conference that covers subjects such as modeling languages, system modelling (digital, analog and mixed signal), power and performance modelling, high level synthesis, high performance computing and parallel programming. There were 2 keynote presentations, 7 lectures and 10 panelists […]

AMIQ Consulting

SVAUnit 2.0 Release is Available

AMIQ is pleased to announce version 2.0 of the SVAUnit framework! Highlights of SVAUnit 2.0 release are: Support for sequence based scenarios Upgraded test setup API Support for complex topologies VPI-related API accessible through a wrapper class pre_test() task is now deprecated UVM compliance reinforced using the Verissimo SystemVerilog Testbench Linter SNUG-2015 paper included Let’s go […]

AMIQ Consulting

How to Verify SystemVerilog Assertions with SVAUnit

A version of this article, titled SystemVerilog Assertions Verification with SVAUnit, was presented at CDNLive EMEA 2015 by Andra Socianu and Ionut Ciocirlan. Intro SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizeable, non-intrusive, coverable), we must verify they […]