Stefan Birman

How To Customize UVM Sequencer’s Arbitration Policy

This post shows how you can implement a custom sequencer arbitration policy in UVM. The example considers a sequence that contains a field called seq_type: typedef enum {MASTER_SEQ, REQ_SEQ, CNFRM_SEQ, ACK_SEQ, REDO_SEQ, DATA_SEQ } ex_seq_type_t; class ex_base_sequence extends uvm_sequence#(ex_sequence_item); ex_seq_type_t seq_type; // this field is used by the arbitration scheme …….. endclass The arbitration policy […]

Teo Vasilache

How to Align SystemVerilog-to-SystemC TLM Transactions Definitions

This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]

Teo Vasilache

How to Export Functional Coverage from SystemC to SystemVerilog

This post presents a way to collect functional coverage from SystemC models using SystemVerilog covergroups and UVM-ML/UVM-Connect. Functional coverage is not standardized yet in SystemC, but there is a workaround for the case of mixed-language(SystemC/SystemVerilog) verification environments. This workaround makes use of covergroups from SystemVerilog and TLM transactions from SystemC and SystemVerilog. When a sampling […]

AMIQ Education Program

Open Source Summer School Labs

The last Digital Circuits Simulation and Verification summer school made me wonder: why restrict access to the labs to only those students that can join the summer course? why not give access to the labs to any student that wished to take the course but couldn’t join due to various reasons? That is why I […]

Recommended Articles

Recommended Articles – June 2017

UVM provides callbacks mechanism that allows one to expand code’s functionality. Munjal explains advanced usage of callbacks in UVM. You might remember, from the highlights of DVCon US 2017 conference, that we recommended a paper about constrained random and dynamic seed manipulation (“Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding […]

Horia-Răzvan Enescu

How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)

In this post I show how to use the streaming operators to unpack data into variables or data structures in SystemVerilog. This is the second part of a 3-post series on data packing/unpacking operations and the natural follow-up to the first part that focuses on packing data using streaming operators. The unpacking operation is the […]