Recommended Articles

Recommended Articles – April 2017

There are multiple ways of connecting a SystemVerilog interface instance to a virtual interface inside the verification environment. Cristian, described two ways of doing just that. One good old simple way when having just one interface instance and another one for multiple instances. CFSVision: UVM: How to Pass a Virtual Interface from Testbentch to Environment […]

Recommended Articles

Recommended Articles – February 2017

Solving sudoku is fun. Solving sudoku using SystemVerilog is both fun and instructive. In a 2015 article, Keisuke Shimizu from ClueLogic, provided a SystemVerilog solution for solving sudoku. In the 2017 version he provides a different solution that makes use of “unique” SystemVerilog keyword. Read all about it here: Hidden Gems of SystemVerilog – 4. […]

Andrei Apostoae

SVAUnit 3.2 Release is Available

AMIQ is pleased to announce version 3.2 of the SVAUnit framework! Highlights of SVAUnit 3.2 are: Added an SVAUnit User Guide with complete examples Added setup_test() task Updated checks API Fixed check evaluation timing to be more accurate Fixed printed messages Support for HTML regression report Fixed assertion registration issue Let’s go through the details […]

Recommended Articles

Recommended Articles – January 2017

SystemVerilog standard provides structure and union data types. Jason Yu, from Intel, has tried to use them for RTL design and he shared his experience via this VerilogPro article: Using SystemVerilog Structures and Unions in a Design. AMIQ Consulting created an UVM/SystemVerilog application that exports existing UVM register models to an IP-XACT file in order […]

Eduard Vișinescu

UVM Register Model to IP-XACT Application

This post presents a simple application for exporting existing UVM/SystemVerilog register models to an IP-XACT file. You can use this application to generate IP-XACT models from existing UVM register models in order to ease IP-XACT adoption. The application is available for free under the Apache License 2 and it can be downloaded from GitHub uvm_reg_to_ipxact […]

Stefan Birman

Functional Coverage Patterns: The Counter

This post explains the functional verification of counters and it is part of a series of posts exploring functional coverage patterns. The first post in the series was Functional Coverage Patterns: Bitwise Coverage. Table of contents What is a Counter? Counter Verification Regarding Synchronicity Reset Value Coverage Clear Value Coverage Overflow and Underflow Policy Coverage […]