- Alexandru Marin
- RnD Team Leader
What Goes where in SystemVerilog?
- October 1st, 2014
- 10 Comments
Is it legal SystemVerilog syntax to declare a class inside a program? What about a function inside a generate block? The table below summarizes the syntactically legal combinations (marked with a check ✔ sign). The number of possible combinations is astonishing. And yet I bet some of the valid combinations have never crossed your mind! On the […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – August 2014
- September 5th, 2014
- No Comments
A library for upgrading SystemVerilog’s capabilities. It handles file, string manipulation routines and more: Verilab: Library code – svlib Verilab: System Verilog, Batteries included A library for enhancing SystemVerilog types and their pseudo-methods: ClueLogic: CluLib Online Documentation ClueLogic: ClueLib code ClueLogic: Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again Article describing how to […]
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