- Stefan Birman
- Verification Engineer
Highlights of DVCon US 2017
- March 13th, 2017
- 1 Comment
DVCon US (Feb 27-Mar 2 2017, San Jose, California) has come to an end after another content-rich edition. Some of the highlights of the technical program AMIQ consultants enjoyed attending are provided below. Hot Topics The main highlight of the conference by far was the emerging Portable Stimulus Standard (PSS), which was presented through a […]
- Ionuț Ciocîrlan
- Verification Engineer
Highlights of DVCon Europe 2016
- November 21st, 2016
- No Comments
The third edition of DVCon Europe (October 19-20, 2016, Munich) has just come to an end. The technical content of the conference was diverse, but three primary areas of interest could be identified: portable stimulus, formal verification, and automotive. While the first two are already common themes in conference programs, the automotive field has recently […]
- Accellera , Conference , DVCon , Highlights , Papers , Tutorials , YAMM
- Ionuț Ciocîrlan
- Verification Engineer
Highlights of DVCon US 2016
- April 7th, 2016
- No Comments
DVCon US (Feb. 29th – Mar 3rd, 2016, San Jose, California) has concluded another successful edition. There were a lot of interesting tutorials, panels and technical sessions, with SV/UVM still being a major focus. There was also a clear emphasis on portable stimuli and the associated standard developed by Accellera’s Portable Stimuli Working Group (PSWG), […]
- Accellera , Conference , DVCon , portable stimulus , SVAUnit , SystemVerilog , Tutorials , UVM
- Stefan Birman
- Verification Engineer
DVCon Europe 2015 Highlights
- November 30th, 2015
- No Comments
Time flies! It’s already 2 weeks since DVCon Europe 2015, long enough for the experience to distill into highlights. AMIQ was involved on multiple levels: sponsoring, exhibiting, contributing a tutorial and last, but not least, AMIQ engineers attending technical presentations. Here are some of the highlights, my highlights. Tutorial Track Accellera&Co. was quite a strong […]
- Stefan Birman
- Verification Engineer
A Conference to Attend: Forum on Specification and Design Languages
- October 12th, 2015
- No Comments
Between 14-15th of September I attended the Forum on Specification and Design Languages(FDL) in Barcelona, a niche conference that covers subjects such as modeling languages, system modelling (digital, analog and mixed signal), power and performance modelling, high level synthesis, high performance computing and parallel programming. There were 2 keynote presentations, 7 lectures and 10 panelists […]
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