Eduard Vișinescu

UVM Register Model to IP-XACT Application

This post presents a simple application for exporting existing UVM/SystemVerilog register models to an IP-XACT file. You can use this application to generate IP-XACT models from existing UVM register models in order to ease IP-XACT adoption. The application is available for free under the Apache License 2 and it can be downloaded from GitHub uvm_reg_to_ipxact […]

Ionuț Ciocîrlan

Highlights of DVCon Europe 2016

The third edition of DVCon Europe (October 19-20, 2016, Munich) has just come to an end. The technical content of the conference was diverse, but three primary areas of interest could be identified: portable stimulus, formal verification, and automotive. While the first two are already common themes in conference programs, the automotive field has recently […]

Ionuț Ciocîrlan

Highlights of DVCon US 2016

DVCon US (Feb. 29th – Mar 3rd, 2016, San Jose, California) has concluded another successful edition. There were a lot of interesting tutorials, panels and technical sessions, with SV/UVM still being a major focus. There was also a clear emphasis on portable stimuli and the associated standard developed by Accellera’s Portable Stimuli Working Group (PSWG), […]

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Recommended Articles – July 2015

Accellera Systems Initiative and IEEE Standards Association announced that UVM1.2 will be delivered as a contribution to the IEEE P1800.2™ standard. Check out Accellera’s press release for more details. UVM is a methodology which creates opportunities. LearnUVMVerification, a new entry on our radar, takes this opportunity and prepares a series of lessons that explore UVM. […]

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Recommended Articles – February 2015

Although February was a 28 days month the Verification community was more active than on a 31 days month. The random generation strategy could be the root cause of long time required to achieve coverage closure. Claudia provides a use case scenario for evaluating coverage closure in relation to generation strategy: AMIQ Blog: A Coverage […]