Cristian Slav

Gotcha: Using “rand” Modifier for Object Handles is not enough!

SystemVerilog allows rand modifier to be used for object handles and the object will be randomized only if it is not null. The “gotcha” is that, depending on the simulator, no error or warning will be issued if you forget to initialize the randomized object. Here is an example that illustrates the gotcha: class item; […]

Cristian Slav

Gotcha: Function Calls in SystemVerilog Constraints

SystemVerilog allows to call functions inside constraints, although, as I found out, it is a sensitive topic. Here is an example: class constraint_container; rand int unsigned a, b, c; function int unsigned get_a(); return a; endfunction function int unsigned value_of(int unsigned value); return value; endfunction constraint a_constraint { a == 5; // I expect “b” […]

Cristian Slav

Gotcha: SystemVerilog’s post_randomize() is Called Top-Down Not Bottom-Up

SystemVerilog classes contain the pre-defined function post_randomize(), which is automatically called at the end of the randomization. One can override this function to do extra processing after randomization. In SystemVerilog post_randomize() is called top-down and not bottom-up! The top-down call of post_randomize() is counter-intuitive, especially for those of you in love with e-Language, and it […]

Cristian Slav

How to Inspect Ethernet Packet Streams with Wireshark

Many protocol stacks in SoCs are based on the IEEE 802.3 Ethernet protocol as the data link layer, while the upper layers can be standard or application specific. Therefore, verification engineers have to inspect and debug Ethernet packet streams generated or monitored by the verification environment. This article shows how to connect the Wireshark network […]

Cristian Slav

How to Stop the Simulation on `uvm_error

The default behavior of `uvm_error is to continue the simulation once the message is reported. Although one can argue over Accelera’s default choice, there are ways to stop the simulation on `uvm_error. I’ve tested them with UVM 1.1d and UVM 1.2 releases. Using Simulator Arguments Major simulators support the +uvm_set_action command-line argument to set a […]