Recommended Articles

Recommended Articles – December 2020

Specman and e-language abound in features, some of them are well known some others less known. In my last article, I focus on a less known feature which can be called as string templates In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, papers and the list of blogs we periodically scan […]

Aurelian Ionel Munteanu

String Templates in E-Language

Learning programming languages is like learning a foreign language. It has words, syntax, grammar and meaning. If you don’t use a foreign language for a long time it might become difficult to remember some of the words. The same happens with programming languages. Keywords or specific language constructs might be difficult to recall if you […]

Recommended Articles

Recommended Articles – November 2020

AMIQ has published a new set of verification resources. Cheatsheets for SystemVerilog and for SystemVerilog Assertions. When in need, every verification engineer now has a reference where to quickly search for basic information. SystemVerilog and SVA Cheatsheet Manish, from Learn UVM Verification, continues his series on UVM RAL. This time he shows how to implement […]

Aurelian Ionel Munteanu

SystemVerilog and SVA Cheatsheet

Have you ever missed a SystemVerilog or an SVA cheatsheet? I surely did and so did my colleagues. As programmers, many times we want just a quick preview of a specific language construct and not to read the full manual. Starting today, instead of browsing through hundreds of pages of the SystemVerilog LRM you can […]

Recommended Articles

Recommended Articles – October 2020

AMIQ has released a new UVC that facilitates register accesses. It is called Register Agent: Register Agent: A UVC for Register Access. Manish from Learn UVM Verification explains why we need a UVM Register Abstraction Layer: Why UVM RAL is needed?. Cadence released a new feature that allows you to integrate Python code into e-language. […]

Recommended Articles

Recommended Articles – September 2020

Did you know that you can match strings using regular expressions from within SystemVerilog code? UVM implements a function called uvm_re_match. My colleague, Florin Oancea, explains how to use it and what you should pay attention at: How to Match Strings in SystemVerilog Using Regular Expressions In the August edition of the recommended articles I […]