Teo Vasilache

How to Align SystemVerilog-to-SystemC TLM Transactions Definitions

This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]

Teo Vasilache

How to Export Functional Coverage from SystemC to SystemVerilog

This post presents a way to collect functional coverage from SystemC models using SystemVerilog covergroups and UVM-ML/UVM-Connect. Functional coverage is not standardized yet in SystemC, but there is a workaround for the case of mixed-language(SystemC/SystemVerilog) verification environments. This workaround makes use of covergroups from SystemVerilog and TLM transactions from SystemC and SystemVerilog. When a sampling […]

Teo Vasilache

How To Automate Code Coverage analysis with Coverage Lens

Sometimes code coverage is required to finalize the verification. By running only random tests most designs will be left with uncovered sections. Trying to fill up the last bits of code coverage you end up either writing directed tests to reach corner cases, or excluding certain “unreachable” sections from coverage statistics. Writing directed tests to […]

Teo Vasilache

YAMM 2.0 Release is Available

Amiq is pleased to announce the release of the YAMM 2.0! The highlight of this release is a C++ implementation that provides the same API as the SystemVerilog one. Download Integrate YAMM with your C++ project Performance SystemVerilog Updates Roadmap Download You can download the YAMM library from GitHub. For getting up to speed you […]