- AMIQ Consulting
- Verification Engineer
SystemVerilog and VHDL Grammars in HTML format
- April 30th, 2018
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We share with the verification community the SystemVerilog and VHDL language grammars in browsable HTML format. The HTML grammars are based on SystemVerilog LRM 2012 (IEEE Std 1800TM-2012) and VHDL LRM 2008 (IEEE Std 1076TM-2008). You can browse these online on their dedicated page Resource > Grammars. You can also download them for off-line use […]
- AMIQ Consulting
- Verification Engineer
How To: Alternative Ways to Implement Bitwise Coverage
- January 15th, 2018
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In a previous post, Stefan provided implementations for several bitwise coverage patterns. In this post I will show an alternative way of implementing a couple of them, avoiding the usage of loops to iterate through all bits. Walking 1 and Walking 0 Coverage covergroup walking1_cg with function sample(bit [WIDTH-1:0] x); walking1_cp: coverpoint $clog2(x) iff ($onehot(x)) […]
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CoverageLens 2.0 Release
- December 6th, 2017
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Coverage Lens (CL) is a C++ utility that checks if a specified set of RTL code coverage items (e.g. statement, condition etc.) is covered by querying an UCIS compliant coverage database. The main functionality is described in the How To Automate Code Coverage analysis with Coverage Lens article. CoverageLens 2.0 release includes support for functional […]
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- Verification Engineer
How to Avoid Parameter Creep for Parameterizable Agents and Interfaces
- November 13th, 2017
- 6 Comments
For configurable protocols, it is useful to have a single agent which can adapt to any protocol configuration. If the agent and the interface are parameterized, having a large number of configuration options will require using many parameters. This can quickly lead to parameter creep: explicitly specifying and propagating all the parameters throughout the environment. […]
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How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)
- June 23rd, 2017
- 6 Comments
In this post I show how to use the streaming operators to unpack data into variables or data structures in SystemVerilog. This is the second part of a 3-post series on data packing/unpacking operations and the natural follow-up to the first part that focuses on packing data using streaming operators. The unpacking operation is the […]
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How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<)
- May 29th, 2017
- 19 Comments
The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures. This post is the first in a series of tutorials about packing and unpacking in SystemVerilog. The article’s sections are: Introduction 1. Pack bytes […]
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