Blog | AMIQ Consulting

AMIQ Consulting
Verification Engineer

SystemVerilog and VHDL Grammars in HTML format

April 30th, 2018
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We share with the verification community the SystemVerilog and VHDL language grammars in browsable HTML format. The HTML grammars are based on SystemVerilog LRM 2012 (IEEE Std 1800TM-2012) and VHDL LRM 2008 (IEEE Std 1076TM-2008). You can browse these online on their dedicated page Resource > Grammars. You can also download them for off-line use […]

IEEE1800 Standard , SystemVerilog , SystemVerilogAssertion , Verilog , VHDL

AMIQ Consulting
Verification Engineer

amiq_i2c – ‘e’ Verification Component for I2C Protocol

October 7th, 2016
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AMIQ released the amiq_i2c eVC (e-Language Verification Component) on GitHub The eVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_i2c eVC is to model the I2C protocol, supporting all the features of the I2C protocol such as: multiple masters multiple slaves arbitration using SDA line […]

e-Language , functional verification , GitHub , VIP

AMIQ Consulting
Verification Engineer

Gotcha: Using a==b==c in SystemVerilog Constraints

September 30th, 2015
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Looking over verification forums, I found a thread where the author was wondering how does a==b==c constraint get evaluated since the result was not the one he was expecting. The scenario is like this: three variables need to be randomized and you want to constraint them to the same value. If you are thinking to […]

gotcha , SystemVerilog

AMIQ Consulting
Verification Engineer

SVAUnit 2.0 Release is Available

June 30th, 2015
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AMIQ is pleased to announce version 2.0 of the SVAUnit framework! Highlights of SVAUnit 2.0 release are: Support for sequence based scenarios Upgraded test setup API Support for complex topologies VPI-related API accessible through a wrapper class pre_test() task is now deprecated UVM compliance reinforced using the Verissimo SystemVerilog Testbench Linter SNUG-2015 paper included Let’s go […]

functional verification , GitHub , methodology , SNUG , SVAUnit , SystemVerilog , SystemVerilogAssertion

AMIQ Consulting
Verification Engineer

How to Verify SystemVerilog Assertions with SVAUnit

April 29th, 2015
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A version of this article, titled SystemVerilog Assertions Verification with SVAUnit, was presented at CDNLive EMEA 2015 by Andra Socianu and Ionut Ciocirlan. Intro SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizeable, non-intrusive, coverable), we must verify they […]

functional verification , GitHub , how to , methodology , SVAUnit , SystemVerilog , SystemVerilogAssertion , utility library

AMIQ Consulting
Verification Engineer

amiq_dcr – SystemVerilog UVC for DCR Protocol

April 1st, 2015
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AMIQ released the amiq_dcr UVC on GitHub The UVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_dcr UVC is to model the Device Control Register Bus (DCR) protocol, supporting all the features of the protocol such as: 4-cycle minimum read or write transfers extendable by […]

DCR , functional verification , GitHub , SystemVerilog , UVC , UVM , VIP