AMIQ Education Program

Mentoring Young Talent Through Hands-on Applications

Introduction by Stefan Birman This article doesn’t have too much to do with functional verification, but keep reading and you’ll be amazed at what a 3rd year student can achieve with the right kind of guidance. Răzvan was one of our 2016 Verification Summer Course participants. My attention was drawn by his ability to grasp […]

Stefan Birman

Highlights of DVCon US 2017

DVCon US (Feb 27-Mar 2 2017, San Jose, California) has come to an end after another content-rich edition. Some of the highlights of the technical program AMIQ consultants enjoyed attending are provided below. Hot Topics The main highlight of the conference by far was the emerging Portable Stimulus Standard (PSS), which was presented through a […]

Recommended Articles

Recommended Articles – February 2017

Solving sudoku is fun. Solving sudoku using SystemVerilog is both fun and instructive. In a 2015 article, Keisuke Shimizu from ClueLogic, provided a SystemVerilog solution for solving sudoku. In the 2017 version he provides a different solution that makes use of “unique” SystemVerilog keyword. Read all about it here: Hidden Gems of SystemVerilog – 4. […]

Andrei Apostoae

SVAUnit 3.2 Release is Available

AMIQ is pleased to announce version 3.2 of the SVAUnit framework! Highlights of SVAUnit 3.2 are: Added an SVAUnit User Guide with complete examples Added setup_test() task Updated checks API Fixed check evaluation timing to be more accurate Fixed printed messages Support for HTML regression report Fixed assertion registration issue Let’s go through the details […]

Recommended Articles

Recommended Articles – January 2017

SystemVerilog standard provides structure and union data types. Jason Yu, from Intel, has tried to use them for RTL design and he shared his experience via this VerilogPro article: Using SystemVerilog Structures and Unions in a Design. AMIQ Consulting created an UVM/SystemVerilog application that exports existing UVM register models to an IP-XACT file in order […]

Eduard Vișinescu

UVM Register Model to IP-XACT Application

This post presents a simple application for exporting existing UVM/SystemVerilog register models to an IP-XACT file. You can use this application to generate IP-XACT models from existing UVM register models in order to ease IP-XACT adoption. The application is available for free under the Apache License 2 and it can be downloaded from GitHub uvm_reg_to_ipxact […]