Stefan Birman

How To Customize UVM Sequencer’s Arbitration Policy

This post shows how you can implement a custom sequencer arbitration policy in UVM. The example considers a sequence that contains a field called seq_type: typedef enum {MASTER_SEQ, REQ_SEQ, CNFRM_SEQ, ACK_SEQ, REDO_SEQ, DATA_SEQ } ex_seq_type_t; class ex_base_sequence extends uvm_sequence#(ex_sequence_item); ex_seq_type_t seq_type; // this field is used by the arbitration scheme …….. endclass The arbitration policy […]

Stefan Birman

Highlights of ORConf 2017

During September 8-10, 2017, I attended the ORConf conference, which is part of the Wuthering Bytes Festival of Technology. The conference is run by the Free and Open Source Silicon Foundation. There were about 60 participants in total, all with different backgrounds: academia, hobbyists, FPGA-based design, law, software development, embedded system design and business. The […]

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Recommended Articles – September 2017

CVFVision continues the SystemC tutorial with an indepth explanation of the sc_module: Learning SystemC: #002 Module – sc_module FPGA4Student explains how to implement a car parking system in VHDL. Working both with SystemC and SystemVerilog is not always an easy task. Teo from AMIQ facilitates understanding of data structures mirroring between SystemVerilog and SystemC: How […]

Teo Vasilache

How to Align SystemVerilog-to-SystemC TLM Transactions Definitions

This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]

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Recommended Articles – August 2017

New entry on our list FPGA4Student is a website dedicated to provide a lot of source code for various FPGA needs. It’s a good resource for learning how to code in Verilog or VHDL. Here is a comparison between Verilog and VHDL: Explain by Examples. Jason Yu from VerilogPro is set to compare implementation of […]

Teo Vasilache

How to Export Functional Coverage from SystemC to SystemVerilog

This post presents a way to collect functional coverage from SystemC models using SystemVerilog covergroups and UVM-ML/UVM-Connect. Functional coverage is not standardized yet in SystemC, but there is a workaround for the case of mixed-language(SystemC/SystemVerilog) verification environments. This workaround makes use of covergroups from SystemVerilog and TLM transactions from SystemC and SystemVerilog. When a sampling […]