Recommended Articles

Recommended Articles – February 2017

Solving sudoku is fun. Solving sudoku using SystemVerilog is both fun and instructive. In a 2015 article, Keisuke Shimizu from ClueLogic, provided a SystemVerilog solution for solving sudoku. In the 2017 version he provides a different solution that makes use of “unique” SystemVerilog keyword. Read all about it here: Hidden Gems of SystemVerilog – 4. […]

Andrei Apostoae

SVAUnit 3.2 Release is Available

AMIQ is pleased to announce version 3.2 of the SVAUnit framework! Highlights of SVAUnit 3.2 are: Added an SVAUnit User Guide with complete examples Added setup_test() task Updated checks API Fixed check evaluation timing to be more accurate Fixed printed messages Support for HTML regression report Fixed assertion registration issue Let’s go through the details […]

Recommended Articles

Recommended Articles – January 2017

SystemVerilog standard provides structure and union data types. Jason Yu, from Intel, has tried to use them for RTL design and he shared his experience via this VerilogPro article: Using SystemVerilog Structures and Unions in a Design. AMIQ Consulting created an UVM/SystemVerilog application that exports existing UVM register models to an IP-XACT file in order […]

Eduard Vișinescu

UVM Register Model to IP-XACT Application

This post presents a simple application for exporting existing UVM/SystemVerilog register models to an IP-XACT file. You can use this application to generate IP-XACT models from existing UVM register models in order to ease IP-XACT adoption. The application is available for free under the Apache License 2 and it can be downloaded from GitHub uvm_reg_to_ipxact […]

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Recommended Articles – December 2016

Often, it happens that the information about a Design Under Test (DUT) or about its verification is being organized in the form of a table like structure (configurations, registers, operation modes, traffic types, etc.). Imagine if you could automatically create bits of code from an Excel table. How awesome is that! E-language is now able […]

Daniel Ciupitu

To be or not to be a Verification Engineer

A verification engineer builds verification environments used to hunt for hardware design flaws and prove a product will operate as expected. But what does that really mean? Do you have the skills to do this job? And should someone even consider doing it? This post is a follow-up to Stefan’s job description of a verification […]