DVCon Europe 2015 Highlights

Time flies! It’s already 2 weeks since DVCon Europe 2015, long enough for the experience to distill into highlights.
AMIQ was involved on multiple levels: sponsoring, exhibiting, contributing a tutorial and last, but not least, AMIQ engineers attending technical presentations. Here are some of the highlights, my highlights.

Tutorial Track

Accellera&Co. was quite a strong presence, in both tutorial and technical tracks.

Philipp A. Hartmann (Intel), Stephan Schulz (Fraunhofer) and Martin Barnasconi (NXP Semiconductors) presented an in-depth status of the Accellera/SystemC working groups (WG). The SystemC-Verification WG made progress on development of UVM SystemC: Language Reference Manual(LRM) is ready and a beta-version implementation will be released later this year.

This presentation was followed by UVM goes Universal – Introducing UVM in SystemC tutorial delivered by Stephan Schulz and Thilo Vörtler from Fraunhofer IIS/EAS. UVM-SystemC is a clone of the UVM-SystemVerilog, but without the native verification features that SystemVerilog provides (coverage collection and constrained-random generation). It might take a looong time before those features will be added and anyone could imagine why.

Uwe Simm (Cadence) refreshed us on UVM WG activities. He clarified the process of handing over UVM to IEEE-1800.2 WG and how the UVM TLM implementation will be aligned to IEEE 1600-2011 TLM 1.0/2.0 standard by the IEEE 1800.2 TLM Sub WG.

Sharon Rosenberg (Cadence) introduced Portable Stimulus WG, the youngest member of Accellera’s WG family and the next “big thing” in verification. AMIQ is a member of this WG and I would recommend anyone to have a deeper look into this topic here or on Mentor’, Cadence’ or Breker’s pages.

Ionut Ciocirlan and Andra Radu (AMIQ) delivered the “SystemVerilog Assertions Verification” tutorial. The presentation was followed by a passionate discussion on SVA verification using formal methods versus unit testing. A discussion that will probably distill into an article.

I ended the first day of presentations with a portion of Birds-of-a-Feather organized by Accellera. AMIQ was directly interested into this session since we want to donate a register modeling library to the SystemC community. The energetic discussion highlighted the need for more people joining Accellera’s SystemC WGs and contributing with man power.

Technical Track

Avidan Efody (Mentor Graphics) explained why the requirement-based verification (ISO 26262, DO254) and coverage driven verification are not excluding each other, but on the contrary they overlap.

How to ease the interface registration with config database? Uwe Simm (Cadence) gave a simple answer to this question: self registrable interface.

John McGrath (Xilinx) showed a use case of Octave&UVM for AMS verification. This presentation reminded me of AMIQ’s 2014 tutorial and…..I am glad our tutorial helped.

Last, but not least, Tudor Timisescu (Infineon) presented a way to use UVM RAL to verify memories.

Awards

This year AMIQ sponsored Best Paper and Best Poster Awards, beside the conference sponsorship.

The Best Paper Award went to Jonathan Bromley and Kevin Johnston from Verilab for paper Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus.

The Best Poster Award went to Ahmed Yehia and Hans Van der Schoot from Mentor Graphics for poster UVM and Emulation: How To Get Your Ultimate Testbench Acceleration Speed-up.

The Location & Other Adventures

The conference was hosted by Holiday Inn Munich City Centre Hotel, a very good choice given the increased number of participants compared with 2014.

The trip to and back from the conference turned into an adventure because of Lufthansa’s strike. All in all, we made it to the conference and back with five people rerouted, a delay of a day on our way back and about 6 hours spent on a night bus (I presume the road from Munich to Prague is beautiful).

Conclusions

I stick with my 2014’s opinion that participation at DVCon is a must for Design and Verification engineers alike and I encourage anyone to contribute either a paper or a tutorial to make the conference even better.


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