The purpose of the amiq_dcr UVC is to model the Device Control Register Bus (DCR) protocol, supporting all the features of the protocol such as:
- 4-cycle minimum read or write transfers extendable by slave or master
- Handshaking supports clocked asynchronous transfers
- Slave bus timeout inhibit capability
- Privileged and Non-Privileged transfers
The amiq_dcr UVC also includes documentation, self checking tests and usage example.
The amiq_dcr UVC is build on top of Common Agent (cagt) architecture available on GitHub.
Feel free to download, use and contribute.