What Goes where in SystemVerilog?

Comments

Alexandru Marin November 24th, 2014 11:02:26

Hi Shalom,

In this table I chose refer to class properties (as defined in IEEE 1800-2012 section 8.2 Classes Overview), module variables (section 3.3 Modules), struct members etc. as “variables”. Many times I’ve wondered what is the SystemVerilog equivalent of the generic term “field” used in software. I felt that the LRM has a preference for the term variable, so I stuck with that one.

However, strictly speaking of structs, in the same LRM section you mention (7.2 Structures) there is an example using the term field:

struct { bit [7:0] opcode; bit [23:0] addr; } IR; // anonymous structure defines variable IR
IR.opcode = 1; // set field in IR.

and the formal syntax snippet which I’ve quoted entirely below:

data_type ::= // from A.2.2.1
...
| struct_union [ packed [ signing ] ] { struct_union_member { struct_union_member } }
{ packed_dimension }
struct_union_member ::=
{ attribute_instance } [random_qualifier] data_type_or_void list_of_variable_decl_assignments ;
data_type_or_void ::= data_type | void
struct_union ::= struct | union [ tagged ]

also uses the term variable (list of variable declaration assignments).

Best regards,
Alex

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Alexandru Marin November 24th, 2014 12:00:48

Hi Shalom,

Suppose I have a valid SystemVerilog source file containing a single function declaration. This is valid syntax by the following chain of formal syntax rules: source_text, description, package_item, package_or_generate_item_declaration, function_declaration. As per IEEE 1800-2012 section 3.12.1 Compilation units and 3.13 Name spaces paragraph (c) this function will reside in the “compilation-unit scope name space”. As simulators generally have a one-library-per-invocation approach, I’ve chosen to see the “compilation-unit scope name space” as equivalent with the library, and tick these containment combinations in the table (function, task, etc and library). I do agree that it is not rigorous, but I think it better serves the purpose of the table as a quick reference. I will add a note to the original post.

Thanks,
Alex

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Alexandru Marin November 24th, 2014 12:02:19

Hi Idan,

Yes, that is a mistake in the table, thanks for pointing it out.

Alex

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Alexandru Marin March 25th, 2015 14:58:32

Hi Lior,

The table specifies where SystemVerilog constructs may be declared, not instantiated or called. Basically the table states that you cannot declare a program inside another program (unlike, for example modules, which can be imbricated).

Best regards,
Alex

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Alexandru Marin February 24th, 2016 19:19:57

Hi Rima,

Yes, that is a mistake in the table, thanks for pointing it out.

Alex

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Alexandru Marin April 7th, 2020 17:55:41

An interface can be instantiated inside a generate block, however, the table above is about declarations. And as the table states, you cannot declare an interface within a generate.
Regarding the second part of your question, can you please clarify? How and where would you intend to access the interface and its members?

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