Lately, I’ve been playing with the coverage features of SystemVerilog. One thing I wanted to do was to filter out some bins from the auto-generated list of cross bins. I searched the Internet for a solution, but only found similar questions with no clear answers. Therefore, I started to work on this problem and came up with two solutions, which I will share with you.

To better illustrate the problem, let’s assume that we want to generate two variables – one always less than or equal to the other, and collect the valid coverage for the generated value.

```
rand bit[3:0] x, y;
constraint c {
x <= y;
}
```

We will use SystemVerilog coverage constructs like *covergroup*, *coverpoint* and *cross* to confirm that we’ve generated all legal values.

Because we are interested only in values x <= y, we’ll need to have some kind of filtering on the cross coverage bins. As you can notice in the picture above, we must filter 120 bins out of the total of 256 bins. It would be a tedious work to try to exclude them bin by bin. So, here are my solutions:

## Using ‘with’

The simplest way to filter unwanted bins is **‘with’** inside an **ignore_bins** construct:

```
covergroup cover_me;
x_cp : coverpoint x;
y_cp : coverpoint y;
x_y_cross: cross x_cp, y_cp {
ignore_bins ignore_x_values_higher_than_y = x_y_cross with (x_cp > y_cp);
}
endgroup
```

## Using CrossQueueType

The second solution is to use **CrossQueueType**. CrossQueueType is the type of a cross coverage bin. Starting with the SystemVerilog standard 2012 (IEEE1800-2012), you can define a function that returns a queue of type CrossQueueType and use it to define the ignored cross coverage bins.

**Pay attention, the function returns the ignored bins, not the valid ones!**

```
covergroup cover_me;
x_cp : coverpoint x;
y_cp : coverpoint y;
x_y_cross : cross x_cp, y_cp {
function CrossQueueType createIgnoreBins();
// Iterate over all bins
for (int xx=0; xx<=15; xx++) begin
for (int yy=0; yy<=15; yy++) begin
if (xx > yy)
// Ignore this bin
createIgnoreBins.push_back('{xx,yy});
else
// This is a valid bin
continue;
end
end
endfunction
ignore_bins ignore_x_values_higher_than_y = createIgnoreBins();
}
endgroup
```

Unfortunately, not all simulators support the above constructs. I prepared two complete code examples – test_with.sv and test_CrossQueueType.sv, which are ready to be compiled and run. You may want to download them to see what works for you.

There may be other solutions as SystemVerilog is quite complex. In case you have knowledge of other solutions please share them.

## ToddM September 27th, 2014 23:45:21